Memory array for increased bit density and method of forming the same

ABSTRACT

A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.

FIELD OF THE INVENTION

The invention relates to the field of random access memory (RAM) devicesformed using a resistance variable material.

BACKGROUND OF THE INVENTION

Resistance variable memory elements, which include ProgrammableConductive Random Access Memory (PCRAM) elements using chalcogenides,have been investigated for suitability as semi-volatile and non-volatilerandom access memory devices. A typical chalcogenide resistance variablememory element is disclosed in U.S. Pat. No. 6,348,365 to Moore andGilton.

In a typical chalcogenide resistance variable memory element, aconductive material, for example, silver, tin and copper, isincorporated into a chalcogenide glass. The resistance of thechalcogenide glass can be programmed to stable higher resistance andlower resistance states. An unprogrammed chalcogenide variableresistance element is normally in a higher resistance state. A writeoperation programs the element to a lower resistance state by applying avoltage potential across the chalcogenide glass and forming a conductivepathway. The element may then be read by applying a voltage pulse of alesser magnitude than required to program it; the resistance across thememory device is then sensed as higher or lower to define two logicstates.

The programmed lower resistance state of a chalcogenide variableresistance element can remain intact for an indefinite period, typicallyranging from hours to weeks, after the voltage potentials are removed;however, some refreshing may be useful. The element can be returned toits higher resistance state by applying a reverse voltage potential ofabout the same order of magnitude as used to write the device to thelower resistance state. Again, the higher resistance state is maintainedin a semi- or non-volatile manner once the voltage potential is removed.In this way, such an element can function as a semi- or non-volatilevariable resistance memory having at least two resistance states, whichcan define two respective logic states, i.e., at least a bit of data.

One exemplary chalcogenide resistance variable device uses a germaniumselenide (i.e., Ge_(x)Se_(100−x)) chalcogenide glass as a backbone. Thegermanium selenide glass has, in the prior art, incorporated silver (Ag)and silver selenide (Ag_(2+/−x)Se) layers in the memory element. FIG. 1depicts an example of a conventional chalcogenide variable resistanceelement 1. A semiconductive substrate 10, such as a silicon wafer,supports the memory element 1. Over the substrate 10 is an insulatingmaterial 11, such as silicon dioxide. A conductive material 12, such astungsten, is formed over insulating material 11. Conductive material 12functions as a first electrode for the element 1. An insulatingmaterial, 13 such as silicon nitride, is formed over conductive material12. A glass material 51, such as Ge₃Se₇, is formed within via 22.

A metal material 41, such as silver, is formed over glass material 51.An irradiation process and/or thermal process are used to causediffusion of metal ions into the glass material 51. A second conductiveelectrode 61 is formed over dielectric material 13 and metal material41.

The element 1 is programmed by applying a sufficient voltage across theelectrodes 12, 61 to cause the formation of a conductive path betweenthe two electrodes 12, 61, by virtue of a conductor (i.e., such assilver) that is present in metal ion laced glass layer 51. In theillustrated example, with the programming voltage applied across theelectrodes 12, 61, the conductive pathway forms from electrode 12towards electrode 61.

A plurality of resistance variable memory elements can be included in amemory array. In doing so, it is desirable to provide a high density ofmemory elements.

BRIEF SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide a memory array having aplurality of resistance variable memory units and methods for formingthe same. Each memory unit includes a first electrode, a resistancevariable material over the first electrode, and a first second-electrodeover the resistance variable material. The first second-electrode isassociated with the first electrode to define a first memory element.Each memory unit further includes a second second-electrode over theresistance variable material. The second-second electrode is associatedwith the first electrode to define a second memory element.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention willbecome more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawingsin which:

FIG. 1 illustrates a cross sectional view of a conventional resistancevariable memory element;

FIG. 2A depicts a portion of a memory array including memory elementsaccording to an exemplary embodiment of the invention;

FIG. 2B illustrates a cross sectional view of a portion of the memoryarray shown in FIG. 2A taken along line 2A-2A′ and according to anexemplary embodiment of the invention;

FIG. 2C illustrates a cross sectional view of a portion of the memoryarray shown in FIG. 2A taken along line 2A-2A′ and according to anotherexemplary embodiment of the invention;

FIG. 3A depicts a portion of a memory array including memory elementsaccording to another exemplary embodiment of the invention;

FIG. 3B illustrates a cross sectional view of a portion of the memoryarray shown in FIG. 3A taken along line 3A-3A′ and according to anexemplary embodiment of the invention;

FIG. 3C illustrates a cross sectional view of a portion of the memoryarray shown in FIG. 3A taken along line 3A-3A′ and according to anotherexemplary embodiment of the invention;

FIG. 4A depicts a portion of a memory array including memory elementsaccording to another exemplary embodiment of the invention;

FIG. 4B illustrates an enlarged portion of the array of FIG. 4A;

FIG. 5A depicts a portion of a memory array including memory elementsaccording to another exemplary embodiment of the invention;

FIG. 5B illustrates an enlarged portion of the array of FIG. 5A;

FIGS. 6A-6F depict the formation of the memory elements of FIG. 2A atdifferent stages of processing; and

FIG. 7 is a block diagram of a system including a memory elementaccording to an exemplary embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to variousspecific embodiments of the invention. These embodiments are describedwith sufficient detail to enable those skilled in the art to practicethe invention. It is to be understood that other embodiments may beemployed, and that various structural, logical and electrical changesmay be made without departing from the spirit or scope of the invention.

The term “substrate” used in the following description may include anysupporting structure including, but not limited to, a semiconductorsubstrate that has an exposed substrate surface. A semiconductorsubstrate should be understood to include silicon-on-insulator (SOI),silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxiallayers of silicon supported by a base semiconductor foundation, andother semiconductor structures. When reference is made to asemiconductor substrate or wafer in the following description, previousprocess steps may have been utilized to form regions or junctions in orover the base semiconductor or foundation. The substrate need not besemiconductor-based, but may be any support structure suitable forsupporting an integrated circuit, including, but not limited to, metals,alloys, glasses, polymers, ceramics, and any other supportive materialsas is known in the art.

The term “resistance variable material” is intended to include materialsthat can change resistance in response to an applied voltage. Suchmaterials include, as non-limiting examples, chalcogenide glasses,chalcogenide glasses comprising a metal, such as silver, tin, copper,among others; a polymer, such as polymethylphenylacetylene,copperphtalocyanine, polyparaphenylene, polyphenylenevinylene,polyaniline, polythiophene and polypyrrole; and amorphous carbon.

The invention is now explained with reference to the figures, whichillustrate exemplary embodiments and throughout which like referencenumbers indicate like features. FIGS. 2A-2C depict a portion of a memoryarray 200 according to exemplary embodiments of the invention. FIGS. 2Band 2C are cross-sections illustrating a portion of the memory array 200of FIG. 2A taken along line 2A-2A′ and according to alternateembodiments of the invention.

Referring to FIGS. 2A and 2B, the array 200 is supported by a substrate210. Over the substrate 210, though not necessarily directly so, is afirst (e.g., a bottom) electrode 212 for each memory element 101 a, 101b. This electrode 212 is preferably tungsten (W), but may be anyconductive material, such as aluminum, among others. An insulating layer214 is between the first electrodes 212 and can be, for example, siliconnitride (Si₃N₄), a low dielectric constant material, an insulatingglass, or an insulating polymer, but is not limited to such materials.

A stack 240 of layers is formed over the first electrodes 212. The stack240 includes one or more layers of resistance variable material. Thestack 240 can include one or more layers of other materials such as, forexample, metal.

In the exemplary embodiments shown in FIGS. 2A-2C, the memory cell stack240 includes, for example, a chalcogenide material layer 241, atin-chalcogenide layer 242, and an optional metal layer 243. Theinvention, however, is not limited to such embodiments, and the stack240 can include additional or fewer layers of other materials suitablefor forming a resistance variable memory element. For example, the stack240 can include a second chalcogenide material layer (not shown) overthe metal layer 243. The second chalcogenide layer may be a samematerial as the chalcogenide layer 241 or a different material.

In the illustrated embodiments, the chalcogenide material layer 241 ise.g., germanium selenide (Ge_(x)Se_(100−x)). The germanium selenide maybe within a stoichiometric range of about Ge₃₃Se₆₇ to about Ge₆₀Se₄₀.The chalcogenide material layer 241 may be between about 100 Å and about1000 Å thick, e.g., about 300 Å thick. Layer 241 need not be a singlelayer, but may also be comprised of multiple chalcogenide sub-layershaving the same or different stoichiometries. The chalcogenide materiallayer 241 is in electrical contact with the underlying electrodes 212.

Over the chalcogenide material layer 241 is an optional layer ofmetal-chalcogenide 242, such as tin-chalcogenide (e.g., tin selenide(Sn_(1+/−x)Se, where x is between about 1 and about 0)), orsilver-chalcogenide (e.g., silver selenide). It is also possible thatother chalcogenide materials may be substituted for selenium, such assulfur, oxygen, or tellurium. The layer 242 in the exemplary embodimentis a layer of tin-chalcogenide layer and may be about 100 Å to about 400Å thick; however, its thickness depends, in part, on the thickness ofthe underlying chalcogenide material layer 241. The ratio of thethickness of the tin-chalcogenide layer 242 to that of the underlyingchalcogenide material layer 241 should be between about 5:1 and about1:3.

An optional metal layer 243 is provided over the tin-chalcogenide layer242, with silver (Ag) being the exemplary metal. This metal layer 243 isbetween about 300 Å and about 500 Å thick. Over the metal layer 243 aresecond (e.g., top) electrodes 251. The second electrodes 251 can be madeof the same material as the first electrodes 212, but are not requiredto be so formed. In the exemplary embodiment shown in FIGS. 2A and 2B,the second electrodes 251 are preferably tungsten (W).

Although in the illustrated exemplary embodiments of the invention,stack 240 is shown including layers 241, 242, 243, it should beappreciated that one or more of layers 241,242, 243 may be excluded andother layers may be included. Non limiting examples of materials andlayers that can be included in stack 240 and materials for electrodes212, 251 are discussed in various patents and patent applicationsassigned to Micron Technology, Inc., including, but not limited to thefollowing: U.S. patent application Ser. No. 10/765,393; U.S. patentapplication Ser. No. 09/853,233; U.S. patent application Ser. No.10/022,722; U.S. patent application Ser. No. 10/663,741; U.S. patentapplication Ser. No. 09/988,984; U.S. patent application Ser. No.10/121,790; U.S. patent application Ser. No. 09/941,544; U.S. patentapplication Ser. No. 10/193,529; U.S. patent application Ser. No.10/100,450; U.S. patent application Ser. No. 10/231,779; U.S. patentapplication Ser. No. 10/893,299; U.S. patent application Ser. No.10/077,872; U.S. patent application Ser. No. 10/865,903; U.S. patentapplication Ser. No. 10/230,327; U.S. patent application Ser. No.09/943,190; U.S. patent application Ser. No. 10/622,482; U.S. patentapplication Ser. No. 10/081,594; U.S. patent application Ser. No.10/819,315; U.S. patent application Ser. No. 11/062,436; U.S. patentapplication Ser. No. 10/899,010; and U.S. patent application Ser. No.10/796,000, which are incorporated herein by reference.

In the embodiment of FIG. 2B, all layers 241, 242, 243 of the stack 240are blanket layers extending over the array 200. In an alternativeembodiment shown in FIG. 2C, at least a portion of the stack 240 ispatterned. When one or more top layers of the stack 240 are conductive,it is desirable to pattern those layers similarly to the secondelectrodes 251 to avoid the second electrodes 251 being shortedtogether. Specifically, in the embodiment illustrated in FIG. 2C,chalcogenide material layer 241 is a blanket layer over the memory arrayand is shared by all memory elements 201 a, 201 b of the array 200, andoptional metal-chalcogenide layer 242 and optional metal layer 243 arepatterned. Layers 242, 243 are patterned similarly to the secondelectrodes 251, as shown in FIG. 2C. Layers 242, 243 and secondelectrodes 251 are patterned to form longitudinally extending elementstacks 202. While FIG. 2C shows only layers 242, 243, 251 as beingpatterned, it should be appreciated that layer 241 could also bepatterned.

As shown in FIG. 2A, the second electrodes 251 are formed as lines alongthe x (first) direction of a memory array. The first electrodes 212 havea pitch 208, which, for example, is the distance in the y direction fromabout the center of a first electrode 212 b in row n+4 to about thecenter of a first electrode 212 c in row n+5. The second electrodes 251have a pitch 209, which is approximately the same as the pitch 208 ofthe first electrodes 212. The second electrodes 251 are offset byapproximately one half pitch 208 (or 209) from the first electrodes 212.Accordingly, as shown in FIGS. 2A-2C, each first electrode 212 underliesa region 260 between two second electrodes 251. In the exemplaryembodiment of FIGS. 2A-2C, each first electrode 212 underlies a portionof two adjacent second electrodes 251. For example, each first electrode212 of word row n underlies a portion of the two adjacent secondelectrodes 251 (one shown above row n in the y (second) direction and asecond one below row n in the y direction).

The array 200 includes memory elements 201 a, 201 b, each for storing atleast one bit, i.e., a logic 1 or 0. Since each first electrode 212underlies two second electrodes 251, each first electrode 212 isassociated with two memory elements 201 a, 201 b. Accordingly, the bitdensity of the array 200 can be increased over prior art arrays thathave a single first electrode associated with a single second electrodeand thus, a single memory element. During operation, conductive pathways221 a, 221 b are formed, which causes a detectible resistance changeacross the memory elements 201 a, 201 b, respectively.

FIGS. 3A-3C depict a portion of a memory array 300 according toadditional exemplary embodiments of the invention. Specifically, FIG. 3Ashows a portion of a memory array 300. FIGS. 3B and 3C show across-section of the memory array 300 of FIG. 3A taken along the line3A-3A′. The embodiments of FIGS. 3A-3C are similar to those depicted inFIGS. 2A-2C, except that each first electrode 212 is associated withthree second electrodes 351.

As shown in FIG. 3A, the second electrodes 351 are lines along the xdirection. The first electrodes 212 have a pitch 308 in the y direction.The second electrodes lines 351 are arranged on a smaller pitch 309 thanthe first electrodes 212, such that three or more second electrodes 351are associated with each first electrode 212. In the illustratedembodiment, three second electrodes 351 can address each first electrode212, but the array 300 could be configured such that electrodes 351 havean even smaller pitch as compared to the pitch 308 of the firstelectrodes, such that more than three second electrodes 351 can addressa single first electrode 212.

The illustrated array 300 includes memory elements 301 a, 301 b, 301 c,each for storing at least one bit, i.e., a logic 1 or 0. Since eachfirst electrode 212 is addressable by three second electrodes 351, eachfirst electrode 212 is associated with three memory elements 301 a, 301b, 301 c. Accordingly the bit density of the array 300 can be increasedover the embodiment shown in FIGS. 2A-2C.

In the embodiment shown in FIG. 3B all layers 241, 242, 243 of the stack240 are blanket layers and are continuously shared by all memoryelements 301 a, 301 b, 301 c of the array 300. In an alternativeembodiment shown in FIG. 3C, at least a portion of the stack 240 ispatterned by etching. Specifically, in the embodiment illustrated inFIG. 3C, chalcogenide material layer 241 is a blanket layer and isshared by all memory elements 301 a, 301 b, 301 c of the array 300, andtin-chalcogenide layer 242 and metal layer 243 are patterned. The layers242, 243 are patterned similarly to the second electrodes 351. WhileFIG. 3C shows only layers 242, 243 as being patterned, it should beappreciated that layer 241 could also be patterned.

FIGS. 4A-4B depict a portion of a memory array 400 according to anotherexemplary embodiment of the invention. Specifically, FIG. 4A shows aportion of a memory array 400 and FIG. 4B is an enlarged view of theportion of FIG. 4A. The embodiment shown in FIGS. 4A-4B is similar tothose depicted in FIGS. 2A-3C, except that each first electrode 212 isassociated with four second electrodes 451.

As shown in FIG. 4A, the first electrodes 212 have a pitch 408 x in thex direction and 408 y in the y direction. The second electrodes 451 arearranged to have approximately the same pitches 408 x, 408 y, but areoffset from the first electrodes 212 by about one half pitch.Accordingly, the second electrodes 451 have a pitch 409 x, 409 y. Also,it is preferable that the second electrodes 451 directly overlie atleast a portion of the first electrode 212 that they address.Specifically, as shown in FIG. 4B, corners 418 of second electrodes 451a, 451 b, 451 c, 451 d directly overlie corners of a corresponding firstelectrode 212.

The array 400 includes memory elements 401 a, 401 b, 401 c, 401 d eachfor storing at least one bit, i.e., a logic 1 or 0. Since each firstelectrode 212 is addressable by four second electrodes 451, each firstelectrode 212 is associated with four memory elements 401 a, 401 b, 401c, 401 d. Accordingly the bit density of the array 400 can be increasedover the embodiment shown in FIGS. 2A-3C.

A cross-sectional view of the array 400 along line 4A-4A′ would appearsimilar to the cross-sectional views shown in FIGS. 2B and 2C. Secondelectrodes 451 would appear in a same position as the electrodes 251shown in FIGS. 2B and 2C. For simplicity, cross-sectional views of thearray 400 are omitted and reference is made to FIGS. 2B and 2C. Thearray 400 includes stack 240 having layers 241, 242, 241, as representedin FIGS. 2B and 2C. Additionally, the layers 241, 242, 243 can beblanket layers (as represented in FIG. 2B) or a portion of the stack240, e.g., layer 242, 243, can be patterned (as represented in FIG. 2C).

FIGS. 5A-5B depict a portion of a memory array 500 according toadditional exemplary embodiments of the invention. Specifically, FIG. 5Ashows a portion of a memory array 500 and FIG. 5B is an enlarged view ofthe portion of FIG. 5A. The embodiments shown in FIGS. 5A-5B are similarto those depicted in FIGS. 2A-4D, except that each first electrode 212is associated with nine second electrodes 551.

As shown in FIG. 5A, the first electrodes 212 have a pitch 508 x in thex direction and 508 y in the y direction. The second electrodes 551 arearranged on a smaller pitches 509 x in the x direction and 509 y in they direction such that nine second electrodes 551 can address each firstelectrode 212. In the illustrated embodiment, nine second electrodes 551can address each first electrode 212, but the array 500 could beconfigured such that electrodes 551 have different pitches as comparedto the pitches 508 x, 508 y of the first electrodes 212, such thatgreater or fewer than nine second electrodes 551 can address a singlefirst electrode 212.

Also, it is preferable that the second electrodes 451 directly overlieat least a portion of the first electrode 212 that they address.Specifically, as shown in FIG. 5B, corners and/or edges 518 of secondelectrodes 551 a, 551 b, 551 c, 551 f, 551 i, 551 h, 551 g, 551 ddirectly overlie corners of a corresponding first electrode 212. Thewhole of second electrode 551 e directly overlies the first electrode212.

The array 500 includes memory elements 501 a, 501 b, 501 c, 501 d, 501e, 501 f, 501 g, 501 h, 501 i each for storing one bit, i.e., a logic 1or 0. Since each first electrode 212 is addressable by nine secondelectrodes 551, each first electrode 212 is associated with nine memoryelements 501 a, 501 b, 501 c, 501 d, 501 e, 501 f, 501 g, 501 h, 501 i.Accordingly the bit density of the array 500 is increased over theembodiment shown in FIGS. 2A-4B.

A cross-sectional view of the array 500 taken along line 5A-5A′ wouldappear similar to the cross-sectional views shown in FIGS. 3B and 3C.Second electrodes 551 would appear in a same position as the electrodes351 shown in FIGS. 3B and 3C. For simplicity, cross-sectional views ofthe array 500 are omitted and reference is made to FIGS. 3B and 3C. Thearray 500 includes stack 240 having layers 241, 242, 241, as representedin FIGS. 3B and 3C. Additionally, the layers 241, 242, 243 can beblanket layers (as represented in FIG. 3B) or a portion of the stack240, e.g., layer 242, 243, can be patterned (as represented in FIG. 3C).

The formation the memory array 200 (FIGS. 2A-2C) according to oneexemplary embodiment of the invention is now described. No particularorder is required for any of the actions described herein, except forthose logically requiring the results of prior actions. Accordingly,while the actions below are described as being performed in a generalorder, the order is exemplary only and can be altered if desired.Although the formation of only a portion of an array 200 is shown, itshould be appreciated that the memory array 200 can include additionalmemory elements 201 a, 201 b, which can be formed concurrently.

As shown by FIG. 6A, a substrate 210 is initially provided. As indicatedabove, the substrate 210 can be semiconductor-based or another materialuseful as a supporting structure. An insulating layer 214 is formed overthe substrate 210. The insulating layer 214 can be silicon nitride, alow dielectric constant material, or other insulators known in the art,and may be formed by any known method. Preferably, the insulating layer214 (e.g., silicon nitride) does not allow metal ion migration from theoptional metal-chalcogenide layer 242. An opening 214 a in theinsulating layer 214 is made, for instance by photolithographic andetching techniques, exposing a portion of the substrate 210. A firstelectrode 212 is formed within the opening 214 a, by forming a layer ofconductive material over the insulating layer 214 and in the opening 214a. A chemical mechanical polishing (CMP) step is performed to remove theconductive material from over the insulating layer 214. Desirably, thefirst electrode 212 is formed of tungsten, but may be any conductivematerial.

At least one layer of a memory stack 240 is formed over the insulatinglayer 214 and first electrodes 212, as depicted in FIG. 6B. In theillustrated embodiment, a chalcogenide material layer 241 is formed overthe first electrodes 212 and insulating layer 214. Formation of thechalcogenide material layer 241 may be accomplished by any suitablemethod, for example, by sputtering.

When it is desirable to etch one or more layers of the stack 240 (FIG.2C), an etch stop layer 231 is formed over the chalcogenide materiallayer 241. As shown in FIG. 6C, the etch stop layer is patterned toprovide openings 231 a over the layer 241 offset from the firstelectrodes 212. The etch stop layer 231 is chosen to have a highselectivity to the etch chemistry used to etch certain layers of thememory cell stack 240. Accordingly, the particular etch stop layer maydepend on the composition of the memory cell stack 240. In theillustrated embodiment, an exemplary etch stop layer is transparentcarbon, although other materials can be used.

As shown in FIG. 6D, additional layers of the memory stack 240 areformed over the etch stop layer and in opening 231 a. In the illustratedembodiment, an optional metal-chalcogenide layer 242 (e.g.,tin-chalcogenide) is formed over the etch stop layer and in opening 231a and in contact with the chalcogenide material layer 241. Themetal-chalcogenide layer 242 can be formed by any suitable method, e.g.,physical vapor deposition, chemical vapor deposition, co-evaporation,sputtering, among other techniques. An optional metal layer 243 isformed over the tin-chalcogenide layer 242. The metal layer 243 ispreferably silver (Ag), or at contains silver, and is formed to apreferred thickness of about 300 Å to about 500 Å. The metal layer 243may be deposited by any technique known in the art.

When the structure of FIG. 2B is desired, formation of the etch stoplayer 231 is omitted and the layer 242, 243 are formed on the layer 241.

Referring to FIG. 6E, a conductive material is deposited over the metallayer 243 to form a second electrode 251. Similar to the first electrode212, the conductive material for the second electrode 251 may be anymaterial suitable for a conductive electrode. In one exemplaryembodiment the second electrode 251 is tungsten.

As illustrated in FIG. 6F, a photoresist layer 232 (or other mask layer)is deposited over the second electrode 251 layer to define secondelectrodes 251. When the structure of FIG. 2B is desired, only thesecond electrode layer 251 is etched. When the structure of FIG. 2B isdesired, second electrode layer 251 and layers 242, 243 are etched todefine stacks 202. The etching stops at the etch stop layer 231.Desirably, the mask layer 232 is formed to define stacks 202 such thatthe stacks 202 have a width 282, which is larger than the width 281 ofthe opening 231 a. This provides for an alignment margin between themask layers used to define openings 231 a and the photoresist layer 232.

The photoresist layer 232 is removed, leaving one of the structuresshown in FIG. 2B or 2C.

Additional steps may be performed to complete the memory array 200. Forexample, an insulating layer (not shown) may be formed over the secondelectrodes 251. Also, other processing steps can be conducted toelectrically couple the array 200 to peripheral circuitry (not shown)and to include the array 200 in an integrated circuit or processorsystem, e.g., processor system 700 described below in connection withFIG. 7.

The method described above can be used to form any memory array 300(FIGS. 3A-3C), 400 (FIGS. 4A-4B), 500 (FIGS. 5A-5B) according to theinvention. When forming any of the arrays 300, 400, and 500, the secondelectrodes 351, 451, 551 (and optionally layers 242, 243), respectively,are patterned to achieve the respective structures described in FIGS.3A-5B.

FIG. 7 illustrates a processor system 700 which includes a memorycircuit 748, e.g., a memory device, which employs memory array 200constructed according to the invention. The circuit 748 could insteademploy any of memory arrays 300 (FIGS. 3A-3C), 400 (FIGS. 4A-4B), or 500(FIGS. 5A-5B). The processor system 700, which can be, for example, acomputer system, generally comprises a central processing unit (CPU)744, such as a microprocessor, a digital signal processor, or otherprogrammable digital logic devices, which communicates with aninput/output (I/O) device 746 over a bus 752. The memory circuit 448communicates with the CPU 744 over bus 752 typically through a memorycontroller.

In the case of a computer system, the processor system 700 may includeperipheral devices such as a floppy disk drive 754 and a compact disc(CD) ROM drive 756, which also communicate with CPU 744 over the bus752. Memory circuit 748 is preferably constructed as an integratedcircuit, which includes a memory array 200 according to the invention.If desired, the memory circuit 748 may be combined with the processor,for example CPU 744, in a single integrated circuit.

The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the present invention. Modification and substitutions tospecific process conditions and structures can be made without departingfrom the spirit and scope of the present invention. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

1-39. (canceled)
 40. A method of forming a memory array, the methodcomprising the act of: forming at least one memory unit, the act offorming the at least one memory unit comprising: forming a firstelectrode, forming a resistance variable material over the firstelectrode; forming a first second-electrode over the resistance variablematerial, the first second-electrode being associated with the firstelectrode to define a first memory element; and forming a secondsecond-electrode over the resistance variable material, the secondsecond-electrode being associated with the first electrode to define asecond memory element.
 41. The method of claim 40, wherein the acts offorming the first and second second-electrodes comprise formingsecond-electrode lines.
 42. The method of claim 40, wherein the firstand second second-electrodes are formed to be associated with aplurality of memory units.
 43. The method of claim 40, wherein the firstelectrode is formed having a pitch, and wherein the second-electrodesare formed to be offset from the first electrode by about one halfpitch.
 44. The method of claim 40, further comprising the act of forminga third second-electrode over the resistance variable material, thethird second-electrode formed to be associated with the first electrodeto define a third memory element.
 45. The method of claim 44, whereinthe second-electrodes are formed to be associated with a plurality ofmemory units.
 46. The method of claim 44, wherein the acts of formingthe first, second and third second-electrodes comprise formingsecond-electrode lines.
 47. The method of claim 44, wherein the firstelectrode is formed having a first pitch, wherein the second-electrodesare formed having a second pitch, and wherein the first pitch is greaterthan the second pitch.
 48. The method of claim 44, further comprisingthe act of forming a fourth second-electrode over the resistancevariable material, the fourth second-electrode formed to be associatedwith the first electrode to define a fourth memory element.
 49. Themethod of claim 48, wherein the first electrode is formed having a firstpitch in a first direction and a second pitch in a second direction, andwherein the second-electrodes are formed offset from the first electrodeby about one half pitch in each of the first and second directions. 50.The method of claim 48, further comprising the acts of forming fifth,sixth, seventh, eighth, and ninth second-electrodes over the resistancevariable material, each of the fifth, sixth, seventh, eighth, and ninthsecond-electrodes formed to be associated with the first electrode todefine a fifth, sixth, seventh, eighth, and ninth memory elements,respectively.
 51. The method of claim 50, wherein the first electrode isformed having a first pitch, wherein the second-electrodes are formedhaving a second pitch, and wherein the first pitch is greater than thesecond pitch.
 52. The method of claim 50, wherein the first electrode isformed having a first pitch in a first direction and a second pitch in asecond direction, wherein the second-electrodes electrodes are formedhaving a third pitch in the first direction and a fourth pitch in thesecond direction, and wherein the first and second pitches are greaterand the third and fourth pitches.